As new technologies are developed to achieve smaller and smaller integrated circuit geometries, voltage differentials and frequency of operation present problems in circuit design and device selection. One such problem exists where the design technology limits the breakdown voltage of n-type devices. Typically, n-type devices operate more quickly than p-type devices, but are limited in voltage range. As physical geometries decrease there is a resultant decrease in the breakdown voltage of n-type devices. At higher voltages, the breakdown of n-type devices may be violated. It is desireable to design circuits which satisfy the voltage requirements of n-type devices while maintaining performance of the circuit.
Integrated circuits often include a charge pump for controlling the voltage supply of an analog-to-digital converter or memory programming circuit. At smaller geometries, the voltages necessary for control and operation of these voltage supplies is beyond the voltage range of n-type devices. There is a need for a method of handling the supply voltages while maintaining the speed of the circuit and maintaining efficient production.
In the drive to reduce the size of the integrated circuit, it is desirable to minimize the circuitry and logic necessary to incorporate features. Designers seek to optimize the use of a memory in performing reset and other maintenance operations. When a memory is part of the data processing system, it is desirable to use that memory for efficient reset operations. When the memory is a programmable memory there is often an associated charge pump to generate a programming voltage. Prior to use during a reset operation, it is desirable to ensure that any programming voltages have been recovered to a lower voltage level. There is a need for a reset method which uses a programmable memory without corrupting data from that memory.